Z85C3010VSG Datasheet, PDF (52/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
44
AS
CS0
INTACK
AD7–AD0
R/W
Address
Data Valid
CS1
DS
Figure 24. Read Cycle Timing
Write Cycle Timing
Figure 25 shows the write cycle timing. The address on AD7–AD0 and the state of CS0
and INTACK are latched by the rising edge of AS. R/W must be Low to indicate a write
cycle. CS1 must be High for the write cycle to occur DS Low strobes the data into the
SCC.
PS011707-1013
Functional Descriptions