Z85C3010VSG Datasheet, PDF (30/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
22
SCC Data Communications Capabilities
The SCC provides two independent full-duplex programmable channels for use in any
common asynchronous or synchronous data communication protocols; see Figure 9. Each
data communication channel has identical feature and capabilities.
Start
Parity
Stop
Marking Line
Data
Data
Data
Asynchronous
SYNC
Data
SYNC
SYNC
Signal
Data
Monosync
Bisync
Data
CRC1
Data
CRC1
Data
Data
CRC1
External Sync
Flag
Address
Information
Information
SDLC/HDLC/X.25
Figure 9. SCC Protocols
CRC1
Marking Line
CRC2
CRC2
CRC2
CRC2
Flag
Asynchronous Modes
Send and Receive is accomplished independently on each channel with five to eight bits
per character, plus optional even or odd parity. The transmitters can supply one, one-and-
a-half, or two stop bits per character and can provide a break output at any time. The
receiver break-detection logic interrupts the CPU both at the start and at the end of a
received break.
Reception is protected from spikes by a transient spike-rejection mechanism that checks
the signal one-half a bit time after a Low level is detected on the receive data input (RxDA
PS011707-1013
Functional Descriptions