Z85C3010VSG Datasheet, PDF (40/83 Pages) Zilog, Inc. – CMOS SCC Serial Communications Controller

CMOS SCC Serial Communications Controller
Product Specification
32
allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to pre-
vent a FIFO underflow condition).
Write Operation
When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents
of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to
increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate
the overflow. This bit and the FIFO control logic is reset by disabling and reenabling the
FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC
frame, see Figure 14.
0
70
F ADDDD CC F
0
70
F ADDDDCC F
Internal Byte Strobe
Increments Counter
Internal Byte Strobe
Increments Counter
Don’t Load
Counter On
1st Flag
Reset Byte
Counter Here
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
Reset
Byte Counter
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
Figure 14. SDLC Byte Counting Detail
Programming
The SCC contains write registers in each channel that are programmed by the system sep-
arately to configure the functional personality of the channels.
Z85C30
In the SCC, the data registers are directly addressed by selecting a High on the D/C pin.
With all other registers (except WR0 and RR0), programming the write registers requires
two write operations and reading the read registers requires both a write and a read opera-
tion. The first write is to WR0 and contains three bits that point to the selected register.
The second write is the actual control word for the selected register, and if the second
operation is read, the selected read register is accessed. All the SCC registers, including
the data registers, can be accessed in this fashion. The pointer bits are automatically
cleared after the read or write operation so that WR0 (or RR0) is addressed again.
PS011707-1013
Functional Descriptions