Z86D990 Datasheet, PDF (73/102 Pages) Zilog, Inc. – Low-Voltage Micro controllers with ADC

Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Whenever a power-on reset is executed, the IRQ is reset to 00h and disabled.
Before the IRQ accepts requests, it must be enabled by executing an enable inter-
rupts instruction.
Note: IRQ is always cleared to 00h and is in read-only mode until the
first EI instruction that enables the IRQ to be read/write. Setting
the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR bit 7) does not enable the IRQ. Execution of an EI
instruction is required.
For polled processing, IRQ must be initialized by an EI instruction. To properly ini-
tialize the IRQ, the following code is provided:
CLR IMR ; make sure vectored interrupts are disabled
EI
; enable IRQ, otherwise it is read only
; not necessary, if interrupts were previously
; enabled
DI
; disable interrupt handling
IMR is cleared before the IRQ enabling sequence to ensure no unexpected inter-
rupts occur when EI is executed. This code sequence must be executed before
programming the application required values for IPR and IMR.
I/O Port Control Registers
Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and an associated buffer and control logic. Because there are separate input
and output registers associated with each port, writing bits defined as inputs
stores the data in the output register. This data cannot be read as long as the bits
are defined as inputs. However, if the bits are reconfigured as output, the data
stored in the output register is reflected on the output pins and can then be read.
This mechanism allows the user to initialize the outputs before driving their loads.
PS003807-1002
PRELIMINARY