Z86D990 Datasheet, PDF (22/102 Pages) Zilog, Inc. – Low-Voltage Micro controllers with ADC

Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
15
Interrupts
The Z86D99/Z86L99 family allows up to six different interrupts, three external and
three internal, from nine possible sources. The six interrupts are assigned as fol-
lows:
• Three edge-triggered external interrupts (P51, P52, and P53), two of which
are shared with the two analog comparators
• One internal interrupt assigned to the T8 Timer
• One internal interrupt assigned to the T16 Timer
• One internal interrupt shared between the Low-Battery Detect flag and the T1
Timer
Table 3 presents the interrupt types, the interrupt sources, and the location of the
specific interrupt vectors.
Table 3. Interrupt Types, Sources, and Vectors
Name
IRQ₀
IRQ₁
IRQ₂
IRQ₃
IRQ₄
IRQ₅
Notes:
Vector
Source
Location Comments
P52 (F/R), Comparator 2 0,1
External interrupt (P52) is triggered by
either rising or falling edge; internal
interrupt generated by Comparator 2
P53 (F)
is mapped into IRQ₀
2,3
External interrupt (P53) is triggered by
a falling edge
P51 (R/F), Comparator 1 4,5
External interrupt (P51) is triggered by
either a rising or falling edge; internal
interrupt generated by Comparator 1
T16 Timer
is mapped into IRQ₂
6,7
Internal interrupt
T8 Timer
8,9
Internal interrupt
LVD, T1 Timer
10,11
Internal interrupt, LVD flag is
multiplexed with T1 Timer End-of-
Count interrupt
F = Falling-edge triggered; R = Rising-edge triggered.
When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer
1 does not generate an interrupt.
These interrupts can be masked and their priorities set by using the Interrupt
Mask Register (IMR) and Interrupt Priority Register (IPR) (Figure 8.) When more
than one interrupt is pending, priorities are resolved by a priority encoder, con-
trolled by the IPR.
PS003807-1002
PRELIMINARY