Z86D990 Datasheet, PDF (23/102 Pages) Zilog, Inc. – Low-Voltage Micro controllers with ADC

Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
16
EI Instruction
S
Interrupt Request Register
(IRQ,FAH)
R
Power-On Reset (POR)
Figure 8. Interrupt Block Diagram
Reset
Interrupt requests are stored in the Interrupt Request Register (IRQ), which can
also be used for polling. When an interrupt request is granted, the Z8 enters an
“interrupt machine cycle” that globally disables all other interrupts, saves the pro-
gram counter (the address of the next instruction to be executed) and status flags,
and finally branches to the vector location for the interrupt granted. It is only at this
point that control passes to the interrupt service routine for the specific interrupt.
All six interrupts can be globally disabled by resetting the master Interrupt Enable
(bit 7 of the IMR) with a Disable Interrupts (DI) instruction. Interrupts are globally
enabled by setting the same bit with an Enable Interrupts (EI) instruction.
Descriptions of three interrupt control registers—the Interrupt Request Register,
the Interrupt Mask Register, and the Interrupt Priority Register—are provided in
“Register Summary” on page 52. The Z8 family supports both vectored and polled
interrupt handling.
External Interrupt Sources
External sources involve interrupt request lines P51, P52, and P53 (IRQ₂, IRQ₀,
and IRQ₁, respectively.) IRQ₀, IRQ₁, and IRQ₂ are generated by a transition on
the corresponding port pin. As shown in Figure 9, when the appropriate port pin
(P51, P52, or P53) transitions, the first flip-flop is set. The next two flip-flops syn-
chronize the request to the internal clock and delay it by two internal clock peri-
ods. The output of the most recent flip-flop (IRQ₀, IRQ₁, or IRQ₂) sets the
corresponding Interrupt Request Register bit.
PS003807-1002
PRELIMINARY