Z86D990 Datasheet, PDF (21/102 Pages) Zilog, Inc. – Low-Voltage Micro controllers with ADC

Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
14
Z8 Standard Register File
Working
Register
Groups
F _{Control and Status Reg.}
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0 _{I/O Port Registers}
Bank 0
General-Purpose
RAM Registers
Bank F
Banks 2 through C are
Reserved—Not Implemented
(Bank E is also reserved)
Figure 7. Z8 Expanded Register File Architecture
Z8 Expanded Register Files
Group 0, Bank F
Stop Mode
Recovery and
Port Mode
Registers
Group 0, Bank D
Timer
Control
Registers
Clock Circuit Description
The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1
and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping
circuit, and a clock buffer. The oscillator’s input is XTAL1, and the oscillator’s out-
put is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock,
RC, or an external clock source.
Clock Control
The Z8 offers software control of the internal system clock using programming
register bits in the SMR register. This register selects the clock divide value and
determines the mode of STOP Mode Recovery.
The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR
register are set to 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal
to the external clock frequency divided by two.
When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the exter-
nal clock frequency. Refer to Table 53 on page 85 for the maximum clock fre-
quency.
A divide-by-16 prescaler of SCLK and TCLK allows the user to selectively reduce
device power consumption during normal processor execution (under SCLK con-
trol) and/or HALT mode, where TCLK sources counter/timers and interrupt logic.
Combining the divide-by-two circuitry with the divide-by-16 prescaler allows the
external clock to be divided by 32.
PS003807-1002
PRELIMINARY