Z86D990 Datasheet, PDF (51/102 Pages) Zilog, Inc. – Low-Voltage Micro controllers with ADC

Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
44
Triggered Input Mode
The T_IN Triggered Input mode (TMR bits D₅ and D₄ set to 1 and 0, respectively)
causes T₁ to start counting as the result of an external event (see Figure 32). T₁ is
then loaded and clocked by the internal timer clock following the first High-to-Low
transition on the T_IN input. Subsequent T_IN transitions do not affect T₁. In the sin-
gle-pass mode, the Enable bit is reset whenever T₁ reaches its end-of-count. Fur-
ther T_IN transitions have no effect on T₁ until software sets the Enable Count bit
again. In continuous mode, when T₁ is triggered, counting continues until software
resets the Enable Count bit. Interrupt request IRQ₅ is generated when T₁ reaches
its end-of-count.
OSC
+2
T_IN
trigger
P5₂
D
D
Edge
trigger
Internal clock
TMR
D₅ = 1
+4
PRE1 T1
IRQ5
TMR
D₅–D₄ = 11
Figure 32. Triggered Clock Mode
IRQ0
Retriggerable Input Mode
The T_IN Retriggerable Input mode (TMR bits D₅ and D₄ both set to 1) causes T₁ to
load and start counting on every occurrence of a High-to-Low transition on T_IN
(see Figure 32). Interrupt request IRQ₅ is generated if the programmed time inter-
val (determined by T₁ prescaler and counter/timer register initial values) has
elapsed since the last High-to-Low transition on T_IN. In single-pass mode, the
end-of-count resets the Enable Count bit. Subsequent T_IN transitions do not
cause T₁ to load and start counting until software sets the Enable Count bit again.
In continuous mode, counting continues when T₁ is triggered until software resets
the Enable Count bit. When enabled, each High-to-Low T_IN transition causes T₁ to
PS003807-1002
PRELIMINARY