Z86L9900100ZEM Datasheet, PDF (69/70 Pages) Zilog, Inc. – ICEBOX

A
B
C
HIGH TO LOW & LOW TO HIGH
VOLTAGE TRANSLATION
pg8 D_P[7..0]
D_P[7..0]
U1
4
pg3 P_CLK_CE
pg3 P_WR_RD
pg3
nP_PGM
pg3
P_CLR
pg3
P_CLK
pg3
P_TBD1
pg3
P_TBD2
pg3
P_TBD3
CONTROL SIGNAL FOR OTP
PROGRAMM ING
D_P0
D_P1
D_P2
D_P3
D_P4
D_P5
D_P6
D_P7
P_CLK_CE
P_WR_RD
nP_PGM
P_CLR
P_CLK
P_TBD1
P_TBD2
P_TBD3
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
D_Ptv0
D_Ptv1
D_Ptv2
D_Ptv3
D_Ptv4
D_Ptv5
D_Ptv6
D_Ptv7
nP_tvCE
nP_tvOE
nP_tvPGM
P_tvCLR
P_tvCLK
P_tvTBD1
P_tvTBD2
P_tvTBD3
VCC
VCC_I
7
18
31
42
VCCB1
VCCB2
VCCA1
VCCA2
1OE
1DIR
2OE
2DIR
48
1
25
24
P_RD_WR
3
28
34
39
45
GND28
GND34
GND39
GND45
GND4
GND10
GND15
GND21
4
10
15
21
IDT74FCT164245TPA
pg3 P_RD_WR
D
D_Ptv[7..0]
HEADERS FOR OTP
PROGRAMMING SOCKET
ADAP TER
D_Ptv0
D_Ptv2
D_Ptv4
D_Ptv6
P_tvCLR
P_tvCLK
P_tvTBD2
P_tvTBD3
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2 D_Ptv1
4 D_Ptv3
6 D_Ptv5
8 D_Ptv7
10
12
14
16
18
20
22
24
26
28
30
HDR15X2
E
4
3
2
1
FOR USER"S MANUAL ONLY
A
UM005100-IRR0400
A_Ptv[15..0]
HEADERS FOR OTP
PROGRAMMING SOCKET
ADAP TER
A_Ptv0
A_Ptv2
A_Ptv4
A_Ptv6
A_Ptv8
A_Ptv10
A_Ptv12
A_Ptv14
nP_tvCE
nP_tvOE
nP_tvPGM
P_tvTBD1
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2 A_Ptv1
4 A_Ptv3
6 A_Ptv5
8 A_Ptv7
10 A_Ptv9
12 A_Ptv11
14 A_Ptv13
16 A_Ptv15
18
VCC_VPP
20
22
VCC_EPM
VCC_VV
24
VCC_I
26
28
30
HDR15X2
B
HIGH TO LOW VOLT AGE TRANSLATION
A_Ptv0
A_Ptv1
A_Ptv2
A_Ptv3
A_Ptv4
A_Ptv5
A_Ptv6
A_Ptv7
A_Ptv8
A_Ptv9
A_Ptv10
A_Ptv11
A_Ptv12
A_Ptv13
A_Ptv14
A_Ptv15
U2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
48
1
25
24
1OE
1DIR
2OE
2DIR
VCCB1
VCCB2
VCCA1
VCCA2
7
18
31
42
4
10
15
21
GND4
GND10
GND15
GND21
GND28
GND34
GND39
GND45
28
34
39
45
IDT74FCT164245TPA
A_P0
A_P1
A_P2
A_P3
A_P4
A_P5
A_P6
A_P7
A_P8
A_P9
A_P10
A_P11
A_P12
A_P13
A_P14
A_P15
VCC
VCC_I
C
OTP REGI STER FOR MSB
& LSB OF ADD RESS
U3
AD_M[7..0]
AD_M[7..0] pg8
2
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1O1
1O2
1O3
1O4
1O5
1O6
1O7
1O8
2O1
2O2
2O3
2O4
2O5
2O6
2O7
2O8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
AD_M0
AD_M1
AD_M2
AD_M3
AD_M4
AD_M5
AD_M6
AD_M7
AD_M0
AD_M1
AD_M2
AD_M3
AD_M4
AD_M5
AD_M6
AD_M7
7
18
31
42
VCC7
VCC18
VCC31
VCC42
1CLK
1OE
2CLK
2OE
48
1
25
24
P_AL_CLK
P_CLK_CE
P_AH_CLK
P_CLK_CE
P_AL_CLK pg8
P_AH_CLK pg8
28
34
39
45
GND28
GND34
GND39
GND45
GND4
GND10
GND15
GND21
4
10
15
21
PROGRAMMING LOGIC
1
IDT74FCT162374ATPV
Title
SCHEMATIC, Z86L99EMULATION DAUGHTER BOARD
Size
B
Document Number
Rev
A
Date:
Monday, August 14, 2000
Sheet
10 of 11
D
E
Schematic 10