Z8F042AHJ020SG Datasheet, PDF (65/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
48
Table 23. Port A–D Output Control Subregisters (PxOC)
Bit
Field
RESET
R/W
Address
7
6
5
4
3
2
1
0
POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
00H (Ports A-C); 01H (Port D)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the alternate function bit and always disable the drains if
set to 1.
0 = The source current is enabled for any output mode unless overridden by the alternate func-
tion (push-pull output).
1 = The source current for the associated pin is disabled (open-drain mode).
Note: x indicates the specific GPIO port pin number (7–0).
Port A–D High Drive Enable Subregisters
The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the
port A–D Control Register by writing 04H to the Port A–D Address Register. Setting the
bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins
for high current output drive operation. The Port A–D High Drive Enable subregister
affects the pins directly and, as a result, alternate functions are also affected.
Table 24. Port A–D High Drive Enable Subregisters (PxHDE)
Bit
Field
RESET
R/W
Address
7
6
5
4
3
2
1
0
PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
PHDEx
Port High Drive Enabled
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
Note: x indicates the specific GPIO port pin number (7–0).
PS022827-1212
PRELIMINARY
GPIO Control Register Definitions