Z8F042AHJ020SG Datasheet, PDF (232/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
215
Table 128. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic Operation
Address
Mode
dst src
Opcode(s)
Flags
Fetch Instr.
Cycle Cycle
(Hex) C Z S V D H s
s
DA dst
dst  DA(dst)
R
40
* * *X–– 2
2
IR
41
2
3
DEC dst
dst  dst - 1
R
30
–* * *–– 2
2
IR
31
2
3
DECW dst
dst  dst - 1
RR
80
–* * *–– 2
5
IRR
81
2
6
DI
IRQCTL[7]  0
8F
–––––– 1
2
DJNZ dst, RA dst  dst – 1
r
if dst  0
PC  PC + X
0A-FA – – – – – – 2
3
EI
IRQCTL[7]  1
9F
–––––– 1
2
HALT
Halt Mode
7F
–––––– 1
2
INC dst
dst  dst + 1
R
20
–* *––– 2
2
IR
21
2
3
r
0E-FE
1
2
INCW dst
dst  dst + 1
RR
A0
–* * *–– 2
5
IRR
A1
2
6
IRET
FLAGS  @SP
SP  SP + 1
PC  @SP
SP  SP + 2
IRQCTL[7]  1
BF
****** 1
5
JP dst
PC  dst
DA
8D
–––––– 3
2
IRR
C4
2
3
JP cc, dst
if cc is true
PC  dst
DA
0D-FD – – – – – – 3
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS022827-1212
PRELIMINARY
eZ8 CPU Instruction Summary