Z8F042AHJ020SG Datasheet, PDF (145/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
128
– Write to BUFMODE[2:0] to select SINGLE-ENDED or DIFFERENTIAL mode,
plus unbuffered or buffered mode.
– Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in the ADC Control Register 0.
3. Write to the ADC Control Register 0 to configure the ADC for continuous conversion.
The bit fields in the ADC Control Register may be written simultaneously:
– Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device).
– Set CONT to 1 to select continuous conversion.
– If the internal VREF must be output to a pin, set the REFEXT bit to 1. The internal
voltage reference must be enabled in this case.
– Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in ADC Control/Status Register 1.
– Set CEN to 1 to start the conversions.
4. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
– CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation
– An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete
5. The ADC writes a new data result every 256 system clock cycles. For each completed
conversion, the ADC control logic performs the following operations:
– Writes the 13-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:3]}
– Sends an interrupt request to the Interrupt Controller denoting conversion com-
plete
6. To disable continuous conversion, clear the CONT bit in the ADC Control Register to 0.
Interrupts
The ADC is able to interrupt the CPU when a conversion has been completed. When the
ADC is disabled, no new interrupts are asserted; however, an interrupt pending when the
ADC is disabled is not cleared.
PS022827-1212
PRELIMINARY
Operation