Z8F042AHJ020SG Datasheet, PDF (45/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
28
tor address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
The text following provides more detailed information about each of the Stop Mode
Recovery sources.
Table 10. Stop Mode Recovery Sources and Resulting Action
Operating Mode
STOP Mode
Stop Mode Recovery Source
Action
Watchdog Timer time-out when configured Stop Mode Recovery
for Reset
Watchdog Timer time-out when configured Stop Mode Recovery followed by
for interrupt
interrupt (if interrupts are enabled)
Data transition on any GPIO port pin enabled Stop Mode Recovery
as a Stop Mode Recovery source
Assertion of external RESET Pin
System Reset
Debug Pin driven Low
System Reset
Stop Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F082A Series device is configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Stop Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
Note: SMR pulses shorter than specified do not trigger a recovery (see Table 135 on page 233).
In this instance, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1.
Caution: In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the Port pin can
initiate Stop Mode Recovery without being written to the Port Input Data Register or
PS022827-1212
PRELIMINARY
Stop Mode Recovery