Z8F042AHJ020SG Datasheet, PDF (147/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
130
Note:
The offset compensation is performed first, followed by the gain compensation. One bit of
resolution is lost because of rounding on both the offset and gain computations. As a
result the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding
and 10 data bits.

Also note that in the second term, the multiplication must be performed before the divi-
sion by 2¹⁶. Otherwise, the second term incorrectly evaluates to zero.
Caution: Although the ADC can be used without the gain and offset compensation, it does exhibit
nonunity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
ADC Compensation Details
High-efficiency assembly code that performs ADC compensation is available for down-
load on www.zilog.com. This section offers a bit-specific description of the ADC compen-
sation process used by this code.
The following data bit definitions are used:
0–9, a–f = bit indices in hexadecimal
s = sign bit
v = overflow bit
– = unused
Input Data
MSB
LSB
s b a 9 8 7 6 5 4 3 2 1 0 – – v (ADC)
ADC Output Word; if v =
1, the data is invalid
s6543210
Offset Correction Byte
s s s s s 7 6 5 4 3 2 1 0 0 0 0 (Offset) Offset Byte shifted to align
with ADC data
s e d c b a 9 8 7 6 5 4 3 2 1 0 (Gain)
Gain Correction Word
PS022827-1212
PRELIMINARY
Operation