Z8F042AHJ020SG Datasheet, PDF (103/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
86
Bit
[6:5]
TICONFIG
[4]
[3:1]
PWMD
[0]
INPCAP
Description (Continued)
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.
10 = Timer Interrupt only on defined Input Capture/Deassertion Events.
11 = Timer Interrupt only on defined Reload/Compare Events.
Reserved
This bit is reserved and must be programmed to 0.
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event.
1 = Previous timer interrupt is a result of Timer Input Capture Event.
Bit
Field
RESET
R/W
Address
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers, shown in Table 51, enable and disable the
timers, set the prescaler value and determine the timer operating mode.
Table 51. Timer 0–1 Control Register 1 (TxCTL1)
7
6
5
4
3
TEN
TPOL
PRES
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
F07H, F0FH
2
1
0
TMODE
0
0
0
R/W
R/W
R/W
Bit
[7]
TEN
Description
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
PS022827-1212
PRELIMINARY
Timer Control Register Definitions