Z86C83 Datasheet, PDF (42/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
*Default Setting After Reset
0 Port 2 Open-Drain*
1 Port 2 Push-Pull
Port 3 Inputs
0 Digital*
1 Analog
Reserved (Must be 0)
Figure 57. Port 3 Mode Register (F7_H: Write-Only)
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
*Default Setting After Reset
P27- P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
Figure 58. Port 2 Mode Register (F6_H: Write-Only)
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
† Not available for
Z86C82, but must be set to 00.
P00-P03 Mode †
00 Output
01 Input *
1X A11-A8
Reserved (Must be 1)
Reserved (Must be 0)
P04-P06 Mode †
00 Output
01 Input *
1X A15-A12
Figure 59. Port 0 and 1 Mode Register
(F8_H: Write-Only)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0)
Figure 60. Interrupt Priority Register (F9_H: Write-Only)
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
Default Setting After Reset = 00H
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = Software Controlled
IRQ4 = T0
IRQ5 = T1
Inter Edge
00 P31 ↓
01 P31 ↓
10 P31 ↑
11 P31 ↑↓
P32 ↓
P32 ↑
P32 ↓
P32 ↑↓
Figure 61. Interrupt Request Register
(F_AH: Read/Write)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5-IRQ0
(D0 = IRQ0)
† This option must be selected when
ROM code is submitted for Rom Masking;
otherwise, this control bit is disabled
permanently.
1 RAM Protect Enabled †
0 RAM Protect Disabled *
1 Enables Interrupts
0 Disable interrupts *
* (Default setting after RESET.)
Figure 62. Interrupt Mask Register (F_BH: Read/Write)
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