Z86C83 Datasheet, PDF (34/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending
execution in mid-instruction. To do this, the user must
execute a NOP (opcode = FFH) immediately before the
appropriate sleep instruction, that is,
FF
NOP
6F
STOP
FF
NOP
7F
HALT
; clear the pipeline
; enter STOP mode
or
; clear the pipeline
; enter HALT mode
STOP-Mode Recovery (SMR) Register. This register se-
lects the clock divide value and determines the mode of
STOP-Mode Recovery (Figure 34 and Figure 35). All bits
are Write-Only, except bit 7, which is Read-Only. Bit 7 is a
flag bit that is hardware set on the condition of STOP re-
covery and reset by a power-on cycle. Bit 6 controls wheth-
er a low level or a high level is required from the recovery
source. Bit 5 controls the reset delay after recovery. Bits 2,
3, and 4, or the SMR Register, specify the source of the
STOP-Mode Recovery signal. Bits 0 and 1 determine the
timeout period of the WDT. The SMR Register is located in
Bank F of the Expanded Register Group at address 0BH.
When the Stop-Mode Recovery sources are selected in
this register, then SMR2 Register bits D0,D1 must be set
to 0.
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag (Read-Only)
0 POR *
1 Stop Recovery
Figure 34. STOP-Mode Recovery Register (Write-
Only Except Bit D7, Which Is Read-Only)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 35. Stop-Mode Recovery Register 2
([0F] DH: Write-Only)
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The
control selectively reduces device power consumption
during normal processor execution (SCLK control) and/or
HALT mode (where TCLK sources counter/timers and
interrupt logic). This bit is reset to D0 = 0 after a Stop-Mode
Recovery, WDT Timeout, and POR.
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by two. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of
PCON further helps lower EMI (that is, D7 (PCON) = 0, D1
(SMR) = 1). The default setting is zero. Maximum external
clock frequency is 4 MHz when SMR Bit D1 = 1 where
SCLK/TCLK = XTAL.
OSC
÷2
SMR, D1
÷ 16
SCLK
SMR, D0 ^TCLK
Figure 36. SCLK Circuit
34
DS96DZ80203