Z86C83 Datasheet, PDF (40/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
EXPANDED REGISTER FILE CONTROL REGISTERS
()
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF* *
1 ON
External Clock Divide-by-2
0 SCLK/TCLK = XTAL/2*
1 SCLK/TCLK = XTAL
Note: Not used in conjunction with SMR2
Source
* Default Setting After RESET
** Default setting after RESET and
Stop-Mode Recovery
Stop-Mode Recovery Source
000 POR Only and/or External Reset*
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag (Read-Only)
0 POR *
1 Stop Recovery
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after RESET
† XTAL=SCLK/TCLK shown
WDT TAP
00 256 SCLK
01 512 SCLK *
10 1024 SCLK
11 4096 SCLK
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC _*
1 XTAL
Reserved (Must be 0)
Figure 47. Stop-Mode Recovery Register
(Write-Only, except Bit 7 which is Read-Only)
Figure 49. Watch-Dog Timer Mode Register
(Write-Only)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,
P24,P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 48. Watch-Dog Timer Mode Register 2
PCON (F) 00
D7 D6 D5 D4 D3 D2 D1 D0
Comparator
Output Port 3
0 P34 Standard Output*
1 P34 Comparator Output
Reserved (Must be 1.)
0 Port 0 Open-Drain
1 Port 0 Push-Pull*
Reserved (Must be 1.)
* Default setting from Stop-Mode Recovery,
Power-On Reset, and any WDT Reset.
Figure 50. Port Configuration Register (PCON)
(Write-Only)
40
DS96DZ80203