Z86C83 Datasheet, PDF(30/46 Page) Zilog, Inc.

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Z86C83 Datasheet, PDF (30/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

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Z86C83/C84

Z8Â® MCU Microcontrollers

Figure 27 shows the input circuit of the ADC. When

conversion starts the analog input voltage is connected to

the MSB and LSB flash converter inputs as shown in the

Input Impedance CKT diagram. Effectively, shunting 31

parallel internal resistance of the analog switches and

simultaneously charging 31 parallel 0.5 pF capacitors,

which is equivalent to seeing a 400 Ohms input impedance

in parallel with a 16 pF capacitor. Other input stray

capacitance adds about 10 pF to the input load. For input

source resistances up to 2 kOhms can be used under

normal operating condition without any degradation of the

input settling time. For larger input source resistance,

longer conversion cycle time may be required to

compensate the input settling time problem.

CMOS Switch

on Resistance

2-5kâ¦

R Source

C Parasitic

V Ref

C .5 pF

31 CMOS Digital

Comparators

Figure 27. Input Impedance of ADC

Typical Z8 A/D Conversion Sequence

1. Set the register pointer to Extended Bank (C),that is,

SRP #%0C instruction.

2. Next, set ADE flag by loading ADC1 Control Register

Bank (C) Register 9, bit 7. Also, load bits 0-4 of this

same register to select a AVCC or AGND offset value. A

precision voltage divider connected to the A/D

resistive ladder can offset conversion dynamic range

to specified limits within the AVCC and AGND limits. By

loading Bank (C) Register 9, bits 0-4, with the

appropriate value it is possible to select from these

groups:

a. No Offset. The Converter Dynamic range is from

0V to 5.0V for AVCC = 5.0V.

b. 35 Percent AGND Offset. The Converter Dynamic

range is 1.75V - 5.0V for AVCC = 5.0V.

c. 50 Percent AGND Offset. The Converter Dynamic

range is 2.5V - 5.0V for AVCC = 5.0V.

3. Select one of the eight A/D inputs for conversion by

loading Bank (C) Register 8 with the desired attributes:

Bits 0 - 2 select an A/D input, bits 3 and 4 select A/D

conversion (or digital port I/O).

4. Set Bank (C) Register 8, bit 3 to enable A/D

conversion. (This flag can be set concurrently with

step 3.) This flag is automatically reset when the A/D

conversion is completed, so a bit test can be

performed to determine A/D readiness if necessary.

5. Read the A/D result in Bank (C) Register A. Please

note that the A/D result is not valid (indeterminate)

unless ADE flag (Register 9, bit 7) was previously set,

otherwise A/D converter output is tri-stated.

DS96DZ80203

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