Z86C83 Datasheet, PDF (24/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Group
Working Register Group
Note: Default Setting After Reset = 00000000
Figure 17. Register Pointer Register
Register File. The Register File consists of three I/O port
registers, 237 general-purpose registers, 15 control and
status registers, and four system configuration registers in
the Expanded Register Group (Figure 16). The
instructions can access registers directly or indirectly
through an 8-bit address field. This allows a short 4-bit
register address using the Register Pointer (Figure 18). In
the 4-bit mode, the Register File is divided into 16 working
register groups, each occupying 16 continuous locations.
The Register Pointer addresses the starting location of the
active working-register group.
Note: Register Bank E0-EF is only accessed through
working registers and indirect addressing modes.
CAUTION: D4 of Control Register P01M (R251) must
be 0.
R254. The C83/C84 has one extra general-purpose
register located at FEH (R254). It is set to 00H after any
reset.
Stack. The C83/C84 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 236
general-purpose registers. Register R254 cannot be used
for stack.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V_CC voltage-specified operating range. It will
not keep its last state from a V_LV reset if the V_CC drops below
1.8V. This includes Register R254.
Note: Register Bank E0-EF is only accessed through
working register and indirect addressing modes.
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
R15 to R0
F0
7F
70
6F
60
5F
50
4F
40
3F
Specified Working
30
Register Group
2F
20
1F
Register Group 1
10
0F
Register Group 0*
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
R15 to R0
R15 to R4*
I/O Ports*
00
* Expanded Register File Bank (0) is selected
in this figure by handling bits D3 to D0 as "0"
in Register R253 (RP).
R3 to R0*
Figure 18. Register Pointer
RAM Protect. The upper portion of the RAM’s address
spaces %80F to %EF (excluding the control registers) are
protected from reading and writing. The RAM Protect bit
option is mask-programmable and is selected by the
customer when the ROM code is submitted. After the mask
option is selected, the user activates this feature from the
internal ROM code to turn off/on the RAM Protect by
loading either a 0 or 1 into the Interrupt Mask (IMR)
register, bit D6. A 1 in D6 enables RAM Protect.
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