Z86C83 Datasheet, PDF (35/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
STOP-Mode Recovery Source (D2, D3, and D4).
These three bits of the SMR register specify the wake-up
source of the STOP recovery (Figure 37 and Table 12).
When the STOP-Mode Recovery Sources are selected in
this register then SMR2 register bits D0,D1 must be set to
zero. P33-P31 cannot wake up from Stop Mode if the input
lines are configured as analog inputs to the Analog
comparator or Analog-to-Digital Converter since the
Analog Comparator’s are powered down in Stop Mode.
Note: If the Port 2 pin is configured as an output, this
output level will be read by the SMR circuitry.
Table 12. STOP-Mode Recovery Source
SMR:432 Operation
D4 D3 D2 Description of Action
0 0 0 POR and/or external reset recovery
0 0 1 Reserved
0 1 0 P31 transition (not in Analog Mode)
0 1 1 P32 transition (not in Analog Mode)
1 0 0 P33 transition (not in Analog Mode)
1 0 1 P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
STOP-Mode Recovery Delay Select (D5). This bit, if
High, enables the T_POR /RESET delay after Stop-Mode
Recovery. The default configuration of this bit is "1". A
POR or WDT reset will override the selection and cause
the reset delay to occur.
STOP-Mode Recovery Edge Select (D6). A "1" in this bit
position indicates that a high level on the output to the
exclusive Or-Gate input from the selected recovery source
wakes the Z86C83/C84 from STOP mode. A "0" indicates
low-level recovery. The default is 0 on POR. This bit is
used for either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT reset. A "1" in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
Note: A WDT reset out of Stop Mode will also set this bit
to a "1."
STOP-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this
register then SMR Register Bits D2, D3, and D4 must be 0.
Table 13. Stop-Mode Recovery Source
SMR:10
D1 D0
00
01
10
Operation
Description of Action
SMR2 disables source
Logical AND of P20 through P23
Logical AND of P20 through P27
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