Z86C83 Datasheet, PDF (37/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The POR clock source is
selected with bit 4 of the WDT register (Figure 38).
WDT instruction affects the Z (Zero), S (Sign), and V
(Overflow) flags. The WDTMR must be written to within 64
internal system clocks. After that, the WDTMR is write
protected.
Note: WDT time-out while in Stop-Mode will not reset
SMR, PCON, WDTMR, P2M, P3M, Ports 2 and 3 Data
Registers, but will cause the reset delay to occur.
The Power-On Reset (POR) clock source is selected with
bit 4 of the WDTMR. Bits 0 and 1 control a tap circuit that
determines the time-out period. Bit 2 determines whether
the WDT is active during HALT and bit 3 determines WDT
activity during STOP. If bits 3 and 4 of this register are both
set to "1," the WDT is only driven by the external clock
during STOP mode. This feature makes it possible to wake
up from STOP mode from an internal source. Bits 5
through 7 of the WDTMR are reserved (Figure 39). This
register is accessible only during the first 64 processor
cycles (64 SCLKs) from the execution of the first
instruction after Power-On-Reset, Watch-Dog Reset or a
Stop-Mode Recovery. After this point, the register cannot
be modified by any means, intentional or otherwise. The
WDTMR cannot be read and is located in Bank F of the
Expanded Register group at address location 0FH.
/RESET
Clear
CLK
18 Clock RESET
Generator
RESET
WDT Select
(WDTMR)
CK Source
Select
(WDTMR)
XTAL
VCC
3.0V REF.
WDT
M
U
RC
X
OSC.
3.0V Operating
+ Voltage Det.
-
WDT TAP SELECT
128 SCLK
POR
CK CLR
128 256 512 2048
SCLK SCLK SCLK SCLK
WDT/POR Counter Chain
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR D5)
Figure 38. Resets and WDT
37
Internal
RESET
DS96DZ80203