Z86C83 Datasheet, PDF (22/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

Z86C83/C84
Z8^® MCU Microcontrollers
FUNCTIONAL DESCRIPTION
RESET. (Input, Active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) Reset, or external reset.
During POR, and WDT Reset, the internally generated
reset is driving the reset pin Low for the POR time. Any
devices driving the reset line must be open-drain to
avoid damage from a possible conflict during reset
conditions. Pull-up is provided internally.
After the POR time, /RESET is a Schmitt-triggered input.
After the reset is detected, an internal RST signal is
latched and held for an internal register count of 18
external clocks, or for the duration of the external reset,
whichever is longer. Program execution begins at location
000C (hex), 5-10 TpC cycles after the RST is released. For
POR, the reset output time is T_POR.
Program Memory. C83/C84 can address up to 4 KB of
internal Program Memory (Figure 15). The first 12 bytes of
program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that correspond
to the six available interrupts. Bytes 13 to 4095 consist of
on-chip, mask-programmed ROM.
ROM Protect. The 4 KB of Program Memory is mask
programmable. A ROM protect feature will prevent
dumping of the ROM contents from an external program
outside the ROM.
Expanded Register File. The register file has been
expanded to allow for additional system control registers
and for mapping of additional peripheral devices and
input/output ports into the register address area. The Z8
register address space R0 through R15 is implemented as
16 groups of 16 registers per group (Figure 16). These
register banks are known as the Expanded Register File
(ERF). Bits 3-0 of the Register Pointer (RP) select the
active ERF bank. Bits 7-4 of register RP select the working
register group (Figure 17). Four system configuration
registers reside in the ERF address space in Bank F and
eight registers reside in Bank C. The rest of the ERF
addressing space is not physically implemented, and is
open for future expansion.
Note: When using Zilog's Cross Assembler version 2.1 or
earlier, use the LD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.
2048/4096
Location of
First Byte of
Instruction
Executed
After RESET 12
11
10
9
8
Interrupt ⁷
Vector ₆
(Lower Byte)
5
4
Interrupt
Vector ₃
(Upper Byte)
2
1
0
On-Chip
ROM
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
Figure 15. Program Memory Map
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