Z86C83 Datasheet, PDF (39/46 Pages) Zilog, Inc. – Z8 MCU MICROCONTROLLERS

EXPANDED REGISTER FILE CONTROL REGISTERS (0C)
Z86C83/C84
Z8^® MCU Microcontrollers
ADC0 (OC) 8H
DACR1 Bank C, Register 4
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after reset.
Channel Select (bits 2,1,0)
CSEL2
0
0
0
0
1
1
1
1
CSEL1
0
0
1
1
0
0
1
1
CSEL0
0
1
0
1
0
1
0
1
Channel
0*
1
2
3
4
5
6
7
Scan 0 = No action.*
1 = Convert channel then stop.
A_IN/Input/Output Control
0 = No Action (Digital Function)*
1 = Enable Selected Channel
(M₂, M₁, M₀) as analog input on
associated Port P27-P20
Must be 0 0 1
DAC1 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DAC1 Enable
0 Disable
1 Enable
Reserved (Must be 0)
Figure 43. D/A 1 Control Register
Figure 40. ADC Control Register 0 (Read/Write)
ADC1 Bank C, Register 9
D7 D6 D5 D4 D3 D2 D1 D0
Must be 0.
D5 D4
0 0 50 % AGND Offset
1 0 35% AGND Offset
0 1 Reserved
1 1 No Offset
Reserved (Must be 1.)
ADE
0 Disable*
1 Enable
Figure 41. ADC Control Register 1 (Read/Write)
DACR2 Bank C, Register 5
D7 D6 D5 D4 D3 D2 D1 D0
DAC2 Gain
0 0 1X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DAC2 Enable
0 Disable
1 Enable
Reserved (Must be 0)
Figure 44. D/A 2 Control Register
DAC1 Bank C, Register 6
D7 D6 D5 D4 D3 D2 D1 D0
0 = Low Level
1 = High Level
ADR1 (OC) AH
D7 D6 D5 D4 D3 D2 D1 D0
Data
Figure 42. AD Result Register (Read Only)
Figure 45. D/A 1 Data Register
DAC2 Bank C, Register 7
D7 D6 D5 D4 D3 D2 D1 D0
0 = Low Level
1 = High Level
Figure 46. D/A 2 Data Register
DS96DZ80203
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