MT90503 Datasheet, PDF (98/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

ct_c8_a
ct_c8_b
ct_c8
MT90503
Input/
8 Cell Pulse
((P * 1024) / Q)
5 Value
SRTS Buffer
change srts
To TXSAR
Data Sheet
recov_a
recov_b
recov_c
recov_d
recov_e
recov_f
recov_g
recov_h
idclk_a
idclk_b
idclk_c
fnxi
fnxi_cnt[3:0]
Figure 48 - Tx SRTS Clock Recovery Module
Register
0810h
0810h
0810h
0812h
0812h
0814h
0818h
081Ah
Bits
Name
Description
0
enable
’1’ enables Tx SRTS
[1:2]
bus_clk_sel source of timing: ’10’ - ct_c8_a,’11’ - ct_c8_b,’0x’ - follows active
clock, ct_c8_a or _b
[8:13] fnxi_input_select selects source of fnxi see Table 28
0
overflow
set if values sent by Tx SRTS is greater than the number of values
read by the Tx SAR
1
underflow
set if the number of Tx SRTS values is less than that read by the Tx
SAR
[0:1]
Interrupt Enables
[0:15] srts8m8c_div_p P = number of frames in the scheduler
[0:15] srts8m8c_div_q Q = number of channels open
Table 32 - Tx SRTS Registers
4.6.8 External Memory Point Format
Figure 49 on page 99 indicates the format of the circular buffers in external memory that contain SRTS and
adaptive point information. In adaptive clock recovery, a point is the information pertinent to the reception of a single
cell. In SRTS, a point is the information corresponding to reception of an SRTS value (gathered over eight cells). If
the received SRTS value is corrupt (due to errors in the received cells) the valid bit (V) will be 0.
98
Zarlink Semiconductor Inc.