MT90503 Datasheet, PDF (92/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
mclk
ct_c8_a
ct_c8_b
ct_c8
ct_framea
ct_frameb
ct_frame
recov_a
recov_b
recov_c
recov_d
recov_e
recov_f
recov_g
recov_h
ct_netref
mclk
ct_c8_a
ct_c8_b
ct_c8
ct_framea
ct_frameb
ct_frame
recov_a
recov_b
recov_c
recov_d
recov_e
recov_f
recov_g
recov_h
ct_netref
mclk
ct_c8_a
ct_c8_b
ct_c8
ct_framea
ct_frameb
ct_frame
recov_a
recov_b
recov_c
recov_d
recov_e
recov_f
recov_g
recov_h
ct_netref
0880h [13:8]
0880h [3]
Divider
088Ah,
0880h[1:0]
Clock Fre-
quency Checker
0890-0894h
08A0h [13:8]
08A0h [3]
Divider
08AAh,
08A0h[1:0]
Clock Frequency
Checker
08B0-08B4h
08C0h [13:8]
08C0h [3]
Divider
08CAh,
08C0h[1:0]
Clock Frequency
Checker
08D0-08D4h
0880h [2]
50% Duty Cycle
Modifier
0880h[2]
0880h [4]
idclk_a
idclk_valid_a
08A0h [2]
50% Duty
Cycle Modifier
08A0h[2]
08A0h [4]
idclk_b
idclk_valid_b
08C0h [2]
50% Duty
Cycle Modifier
08C0h[2]
08C0h [4]
idclk_c
idclk_valid_c
Figure 44 - Integer Clock Processor
4.6.4 Precise Clocks (pclk)
The MT90503 has two digital PLL (pclk) modules. Using mclk as a source, the module will divide it with a 16-bit
integer and optional 16-bit fraction. The 16-bit fraction allows more precise specification on the output frequency.
Using the optional 16-bit faction in a typical configuration, mclk = 80MHz, pclk_int_a = 10 000 and pclk_a = 8kHz,
will increase the precision from 100 ppm to 1.5 ppm. Also, using the fractional divider will reduce the maximum jitter
to one mclk period (12.5ns for 80MHz mclk). Set pclk_frc to 0 if no jitter insertion by the pclk module desired. The
divider can be programmed dynamically and has a maximum response time of 125µs.
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Zarlink Semiconductor Inc.