MT90503 Datasheet, PDF (203/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
Address: A0Ch
Label: status_ie
Reset Value: 0000h
Label
Bit
Position
Type
Description
h100_clk_a_bad_rol
h100_clk_b_bad_rol
h100_frame_a_bad_rol
h100_frame_b_bad_rol
reserved
0
IE When '1' and the corresponding status bit is '1', an interrupt will
be generated.
1
IE When '1' and the corresponding status bit is '1', an interrupt will
be generated.
2
IE When '1' and the corresponding status bit is '1', an interrupt will
be generated.
3
IE When '1' and the corresponding status bit is '1', an interrupt will
be generated.
15:4
IE Reserved. Always read as "0000_0000_0000"
Table 291 - H.100 Interrupt Enable Register
6.0 Statistics
6.1 TDM statistics
Underrun counter: 16-bit counter that counts the number of underruns detected by TDM interface.
6.2 TX SAR statistics
Percentage of bandwidth utilisation: a register (0510h) which indicates how many mclk cycles were required to treat
the last frame.
Transmitted Cell Counter: 32-bit counter that counts the number of cells transmitted on a particular VC. Each VC
has its own counter in its structure.
6.3 RX SAR statistics
Error reporting structures allow software-based counters for the following errors:
• P-byte absent error
• P-byte framing error
• P-byte range error
• P-byte parity error
• Overrun error
• Underrun error
• AAL1 CRC error
• AAL1 parity error
• Single cell loss
• Multiple cell loss
• Cell misinsertion
203
Zarlink Semiconductor Inc.