MT90503 Datasheet, PDF (64/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
4.3.5 TX_SAR Control Structures
TX_SAR control structures are constructs in control memory which contain ATM cell information. When a frame
event is read from one of the 15 transmit event schedulers, an ATM cell is assembled. The scheduler event
contains the base address that points to the control structure that is used for assembling the ATM cell. The control
structure contains all of the fields that are required for assembling the ATM cell. The destination field in the control
structure is responsible for telling the UTOPIA Module the destination VC of the assembled ATM cell. For detailed
information regarding the destination field, refer to Table 22, 'Description of the Fields for the TX_SAR Control
Structure"‚ on page 65.
Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure shows a functional block diagram of an
example of transmit event scheduler interconnections and pointer flow to the TX_SAR control structure.
Scheduler
List
Pointer to current
Frame in Scheduler
00000h ^{Scheduler 0’s Info}
00008h
00070h
Scheduler 0
Scheduler 0, Frame 0
Scheduler 0, Frame 1
Scheduler 0, Frame 374
Scheduler 0, Frame 1
Event 0
Event 1
Event 63
Base address of control structure from Event 1
TX_SAR Control Structure
Header of the
Structure
tx_sar_read_pnt
TDM Channel 0 Pnt
TDM Channel 1 Pnt
TDM Channel 2 Pnt
TX/RX Circular Buffer Pointer
(Same pointer in Channel Association
Memory and in TX_SAR Control Structure)
TDM Channel Association
Memory (Internal)
TSST 0
TSST 1
TSST 2
TSST 4093
TSST 4094
TSST 4095
Byte read by
TX_SAR
tdm_write_pnt
TX Side
Byte written by
TDM Transmit
RX Side
TDM Channel 1’s Circular
Buffer (in the Data Memory)
Note: All structures are in the Control memory unless otherwise specified
Figure 28 - TX_SAR Event Scheduler Pointer Flow and Control Structure
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