MT90503 Datasheet, PDF (91/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
These modules are ideally suited to dividing down the highly accurate reference clock (f_n) required when
performing SRTS clock recovery.
Register Bits
Name
Description
0880h
0880h
0880h
0880h
0880h
0880h
0882h
0884h
[0] divisor_load_now
[1] divisor_reset
[2] even_duty_cycle_select
[3] input_invert_select
[4] output_invert_select
[13:8] input_source_select
[5:0]
[5:0]
set to load new value
0 for reset, 1 for normal operation
when 1, 50% duty cycle is generated
invert clock before dividing
invert clock after dividing
see Table 28
status registers
interrupt enabling
0886h
[5:0]
manual setting of status registers
0888h
[5:0] ext_loss_source_select
external output of input clock status. See Table 28.
0888h
[6] ext_loss_source_polarity
if set to ’1’, source loss is active high
0888h
[7] output_loss_polarity
if ’1’ output loss is active high
088Ah [15:0] clk_div
denominator of clock divider
0890h [15:0] freqchck_div
denominator of frequency check divider
0892h [15:0] freqchck_max_mclk_cycles
max # of mclk’s between rising edges of the input clock divided by
freqchck_div, if failure occurs, freq_too_low (0882h) will be set.
0894h [15:0] freqchck_min_mclk_cycles
min # of mclk’s between rising edges of the input clock divided by
freqchck_div, if failure occurs, freq_too_high (0882h) will be set.
Note: idclk_b and idclk_c have a corresponding set of registers in the ranges of 08A0h - 08B4h and 08C0h - 08D4h
respectively.
Table 29 - idclk_a Register
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