MT90503 Datasheet, PDF (157/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

Address: 502h
Label: status
Reset Value: 0000h
Label
global_tx_slip
txsarpip_overflow
reserved
MT90503
Data Sheet
Bit
Position
Type
Description
0
ROL Raised when a bad configuration of the offset field in the TX
control structure causes the TX SAR to read data that has
not been written yet.
1
ROL Overflow in the TX SAR data memory access cache. Fatal
chip error.
15:2
RO Reserved. Always read as "0000_0000_0000_00"
Table 156 - TX_SAR Status Register
Address: 504h
Label: status_ie
Reset Value: 0000h
Label
Bit
Position
Type
Description
global_tx_slip_ie
txsarpip_overflow_ie
reserved
0
IE When '1' and the corresponding status bit is '1', an interrupt will be
generated.
1
IE When '1' and the corresponding status bit is '1', an interrupt will be
generated.
15:2
IE Reserved. Always read as ""0000_0000_0000_00"
Table 157 - TX_SAR Interrupt Enable Register
Address: 506h
Label: control1
Reset Value: 0000h
Label
reset_band_per
reserved
Bit
Position
Type
Description
0
PUL Resets the band_per register field.
15:1
RO Reserved. Always read as "0000_0000_0000_000"
Table 158 - TX_SAR Control 1 Register
157
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