MT90503 Datasheet, PDF (114/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
Address: 226h
Label: interrupt2_conf
Reset Value: 0000h
Label
reserved
interrupt2_polarity
Bit
Position
Type
Description
13:0
RW Reserved. Must be "0000_0000_0000_00"
15:14
RW Interrupt polarity and output enable. "00"=active low
(open-collector); "01"=active high (open-collector); "10" =
drive low; "11" = drive high. Drive low or drive high means
that the pin's value will not change regardless of internal
interrupts.
Table 56 - Interrupt2 Configuration Register
Address: 228h
Label: interrupt1_enable
Reset Value: 0000h
Label
Bit
Position
Type
Description
cpureg_interrupt1_enable
0
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
mainreg_interrupt1_enable
1
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
utoreg_interrupt1_enable
2
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
txreg_interrupt1_enable
3
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
rxreg_interrupt1_enable
4
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
miscreg_interrupt1_enable
5
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
wheelreg_interrupt1_enable
6
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
clkreg_interrupt1_enable
7
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
tdmreg_interrupt1_enable
8
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
mastreg_interrupt1_enable
9
RW When '1' and the corresponding interrupt active is
'1', an interrupt will be generated on cpu_int[0].
Table 57 - Interrupt1 Enable Register
114
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