MT90503 Datasheet, PDF (100/233 Pages) Zarlink Semiconductor Inc – 2048VC AAL1 SAR

MT90503
Data Sheet
5.0 Memory
5.1 Memory Overview
The MT90503 requires external memory for two purposes: control and data memory. The control memory contains
information required for: TX_SARs and RX_SARs control structures, transmission schedulers, look up values to
map VCs to RX structures. The control memory also stores data cell FIFO’s. CAS buffers and clock recovery data is
also stored in the control memory. The data memory is employed to store network traffic data for a maximum of
2048 bi-directional TDM channels.
The MT90503 interfaces with the external Data SSRAM via the following pins: 19 address pins (dmem_a), 4
memory bank/chip selection pins (dmem_cs), 16 data pins, (dmem_d), 2 parity pins (dmem_par), 1 R/W(low) pin
used for late write memories (dmem_rw), 2 data memory byte write select pins (dmem_bws) and a memory clock
(mem_clk). The external Control SSRAMs interface pins: 19 address pins (cmem_a), cmem_a[18] can be
configured as a: memory bank/chip selection pin (cmem_cs[1]) or an address pin cmem_a[18], 1 dedicated
memory bank/chip selection pin (cmem_cs[0]), 16 data pins, (cmem_d), 1 R/W(low) pin used for late write
memories (cmem_rw), 2 control memory byte write select pins (cmem_bws).
The data memory supports up to 4 memory banks up to 512 k words per bank determining a data memory limit of
4 MB. The data memory clock speed gamut is 40 MHz to 80 MHz. Note: recommended mem_clk speed is 80 MHz.
The option of a reduced memory capability is also supported. The following SSRAM sizes can be employed:
128 kB, 256 kB, 512 kB and 1 MB. The data bus consists of 18 data bits where two data bits are dedicated as parity
bits. The parity bits are used to detect underruns in the circular buffers generated on the ATM link and data error
detection. The parity check can be disabled to permit non-parity memory compatibility. The MT90503 supports 1, 2,
3 or 4 banks of external memory, each bank having a total capacity ranging from 64 k x 18 bits to 512 k x 18 bits.
Therefore the MT90503 can operate with external memory ranging from 128 kB to 4 MB. The above data memory
configuration is initialised via: Data Memory Parity 0 Register, Data Memory Parity 1 Register and Data Memory
Configuration Register (0248h, 024Ah & 024Ch respectively).
The control memory maximum capacity is 512 k words and supports 2 memory banks. The reduced memory
capability is supported in the same manner as the data memory. However, if all 19 address bits are employed then
the use of 1 memory bank is permitted. Therefore the MT90503 can operate with external control memory ranging
from 128 kB to 1 MB. The MT90503 dose not use the parity bits supplied by the control memory. Parity bits can be
generated within the MT90503 and are used for error detection. The above control memory configuration is
initialised via: Control Memory Parity 0 Register, Control Memory Parity 1 Register and Control Memory
Configuration Register (0240h, 0242h & 0244h respectively).
The MT90503 supports both Pipelined and Flow Through SSRAM employing either: ‘normal’ or ‘Zero Bus
Turnaround’ (ZBT) operation. When PECL clock is employed ‘Late-Write’ is supported in ‘normal’ operation.
The memory clock (mem_clk) interface must be configured to either PECL or TTL. The interface can be initialised
via the ‘CPU Control Register’ address 0100h.
The external memory controller can interface with several types of SSRAM, but they must support synchronous bus
enabling. The SSRAM chip must only enable its data output buffers one cycle after a read (two for pipelined
SSRAM), irrespective of the state of the asynchronous output enable pin. A read is indicated by mem_rw high and
the appropriate mem_cs asserted. The SSRAM can be a registered input type (Synchronous, Synchronous Flow
through or Synchronous Burst) or a registered input/output type (Synchronous pipelined). Although the MT90503
uses synchronous access feature of the memory, it does not use the burst access feature of the memory.
Specific Synchronous SRAM devices may require a turnaround cycle with respect to the bidirectional data bus. The
MT90503 can be configured to insert a turnaround cycle between read access and write access. A turnaround
cycle can be inserted between read access and read access to other memory banks. The turnaround cycle
configuration is initialised via: Control Memory Configuration Register and Data Memory Configuration Register
(0244h & 024Ch respectively). It should be noted that turnaround cycles restrict the memory bandwidth and
therefore the operation MT90503. Maximum throughput is achieved with full clock speed on MCLK and without
pipelined synchronous RAM and turnaround cycles.
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