XQ4010E-4PG191M Datasheet, PDF (9/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-4
Symbol
Write Operation Description
Size Min Max Min Max
T_WCS Address write cycle time (clock K period)
16x2
T_WCTS
32x1
T_WPS Clock K pulse width (active edge)
16x2
T_WPTS
32x1
T_ASS Address setup time before clock K
16x2
T_ASTS
32x1
T_AHS Address hold time after clock K
16x2
T_AHTS
32x1
T_DSS D_IN setup time before clock K
16x2
T_DSTS
32x1
T_DHS D_IN hold time after clock K
16x2
T_DHTS
32x1
T_WSS WE setup time before clock K
16x2
T_WSTS
32x1
T_WHS WE hold time after clock K
16x2
T_WHTS
32x1
T_WOS Data valid after clock K
16x2
T_WOTS
32x1
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
14.4 - 15.0 -
14.4 - 15.0 -
7.2 1 ms 7.5 1 ms
7.2 1 ms 7.5 1 ms
2.4
-
2.8
-
2.4
-
2.8
-
0
-
0
-
0
-
0
-
3.2
-
3.5
-
1.9
-
2.5
-
0
-
0
-
0
-
0
-
2.0
-
2.2
-
2.0
-
2.2
-
0
-
0
-
0
-
0
-
8.8
-
- 10.3
10.3 -
- 11.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Write Operation Description
Size⁽¹⁾
-3
Min Max
-4
Min Max
T_WCDS
Address write cycle time (clock K period)
16x1
T_WPDS Clock K pulse width (active edge)
16x1
T_ASDS
Address setup time before clock K
16x1
T_AHDS
Address hold time after clock K
16x1
T_DSDS
D_IN setup time before clock K
16x1
T_DHDS D_IN hold time after clock K
16x1
T_WSDS WE setup time before clock K
16x1
T_WHDS WE hold time after clock K
16x1
T_WODS Data valid after clock K
16x1
Notes:
1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
14.4
15.0
7.2 1 ms 7.5 1 ms
2.5
-
2.8
-
0
-
0
-
2.5
-
2.2
-
0
-
0
-
1.8
-
2.2
-
0
-
0.3
-
-
7.8
- 10.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS021 (v2.2) June 25, 2000
www.xilinx.com
9
Product Specification
1-800-255-7778