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XQ4010E-4PG191M Datasheet, PDF (34/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX
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QPRO XQ4000E/EX QML High-Reliability FPGAs
R
Pin Description
Bound
PG191 CB196 Scan
I/O
V5
P136 457
I/O
V4
P137 460
I/O
U5
P138 463
I/O
T6
T139 446
I/O_(D1)
V3
P140 469
I/O_(RCLK-/BUSY/RDY)
V2
P141 472
I/O
U4
P142 475
I/O
T5
P143 478
I/O_(D0*_DIN)
U3
P144 481
SGCK4_(DOUT*_I/O)
T4
P145 484
CCLK
V1
P146
-
VCC
R4
P147
-
TDO
U2
P148
-
GND
R3
P149
-
I/O_(A0*_WS)
T3
P150
2
PGCK4_(I/O*_A1)
-
U1
P151
5
-
P152(1)
-
I/O
P3
P153
8
I/O
R2
P154
11
I/O_(CS1*_A2)
T2
P155
14
I/O_(A3)
N3
P156
17
I/O
P2
P157
20
I/O
T1
P158
23
I/O
R1
P159
26
I/O
N2
P160
29
GND
M3
P161
-
I/O
P1
P162
32
I/O
N1
P163
35
I/O_(A4)
M2
P164
38
I/O_(A5)
M1
P165
41
I/O
L3
P166
44
I/O
L2
P167
47
I/O
L1
P168
50
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Pin Description
Bound
PG191 CB196 Scan
I/O
K1
P169
53
I/O_(A6)
K2
P170
56
I/O_(A7)
K3
P171
59
GND
K4
P172
-
VCC
J4
P173
-
I/O_(A8)
J3
P174
62
I/O_(A9)
J2
P175
65
I/O
J1
P176
68
I/O
H1
P177
71
I/O
H2
P178
74
I/O
H3
P179
77
I/O_(A10)
G1
P180
80
I/O_(A11)
G2
P181
83
I/O
F1
P182
86
I/O
E1
P183
89
GND
G3
P184
-
I/O
F2
P185
92
I/O
D1
P186
96
I/O
C1
P187
98
I/O
E2
P188 101
I/O_(A12)
F3
P189 104
I/O_(A13
-
D2
P190
107
-
P192(1)
-
I/O
E3
P193 113
I/O_(A14)
C2
P194 116
SGCK1(A15*I/O)
B2
P195 119
VCC
D3
P196
-
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Additional XQ4010E Package Pins
CB196
P5
P192
No Connect Pins
P54
P103
-
-
P152
-
34
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
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