XQ4010E-4PG191M Datasheet, PDF (14/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
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-4
Symbol
Description
Device
Min Max Min Max Units
Propagation Delays (TTL Inputs)⁽¹⁾
T_PID Pad to I1, I2
All devices
-
2.5
-
3.0
ns
T_PLI Pad to I1, I2 via transparent input latch, no delay All devices
-
3.6
-
4.8
ns
T_PDLI Pad to I1, I2 via transparent FCL and input latch,
XQ4005E
-
-
-
10.8 ns
with delay
XQ4010E
-
10.8
-
11.0 ns
XQ4013E
-
11.2
-
11.4 ns
XQ4025E
-
-
-
13.8 ns
Propagation Delays (CMOS Inputs)⁽¹⁾
T_PIDC Pad to I1, I2
All devices
-
4.1
-
5.5
ns
T_PLIC Pad to I1, I2 via transparent input latch, no delay All devices
-
8.8
-
6.8
ns
T_PDLIC Pad to I1, I2 via transparent FCL and input latch,
XQ4005E
-
-
-
16.5 ns
with delay
XQ4010E
-
14.0
-
17.5 ns
XQ4013E
-
14.4
-
18.0 ns
XQ4025E
-
-
-
20.8 ns
Propagation Delays (TTL Inputs)
T_IKRI Clock (IK) to I1, I2 (flip-flop)
T_IKLI Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times⁽²⁾
All devices
-
2.8
-
5.6
ns
All devices
-
4.0
-
6.2
ns
T_IKPI
T_IKPID
T_IKEC
T_IKECD
Pad to clock (IK), no delay
Pad to clock (IK), with delay
Clock enable (EC) to clock (K), no delay
Clock enable (EC) to clock (K), with delay
All devices 0
-
0
-
ns
All devices 0
-
0
-
ns
All devices 1.5
-
1.5
-
ns
All devices 0
-
0
-
ns
Notes:
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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DS021 (v2.2) June 25, 2000
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