XQ4010E-4PG191M Datasheet, PDF (6/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Symbol
Description^(1,2)
Device
-3
-4
Max Max Units
T_WAF Full length, both pull-ups, inputs from IOB I-pins
XQ4005E
XQ4010E
-
9.5
ns
9.0 15.0 ns
XQ4013E 11.0 16.0 ns
XQ4025E
- 18.0 ns
T_WAFL Full length, both pull-ups, inputs from internal logic
XQ4005E
- 12.5 ns
XQ4010E 11.0 18.0 ns
XQ4013E 13.0 19.0 ns
XQ4025E
- 21.0 ns
T_WAO Half length, one pull-up, inputs from IOB I-pins
XQ4005E
- 10.5 ns
XQ4010E 10.0 16.0 ns
XQ4013E 12.0 17.0 ns
XQ4025E
- 19.0 ns
T_WAOL Half length, one pull-up, inputs from internal logic
XQ4005E
- 12.5 ns
XQ4010E 12.0 18.0 ns
XQ4013E 14.0 19.0 ns
XQ4025E
- 21.0 ns
Notes:
1. These delays are specified from the decoder input to the decoder output.
2. Fewer than the specified number of pull-up resistors can be used, if desired. Using fewer pull-ups reduces power consumption but
increases delays. Use the static timing analyzer to determine delays if fewer pull-ups are used.
6
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DS021 (v2.2) June 25, 2000
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