XQ4010E-4PG191M Datasheet, PDF (5/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
The following guidelines reflect worst-case values over the
recommended operating conditions.
-3
-4
Symbol
Description
Device
Max Max
TBUF Driving a Horizontal Longline (LL):
T_IO1 I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active.⁽¹⁾
XQ4005E
XQ4010E
-
5.0
6.4 8.0
XQ4013E 7.2 9.0
XQ4025E
- 11.0
T_IO2 I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain.⁽¹⁾
XQ4005E
XQ4010E
-
6.0
6.9 10.5
XQ4013E 7.7 11.0
XQ4025E
- 12.0
T_ON T going Low to LL going from resistive pull-up or floating High to
active Low. TBUF configured as open-drain or active buffer with
I = Low.⁽¹⁾
XQ4005E
XQ4010E
XQ4013E
-
7.0
7.3 8.5
7.5 8.7
XQ4025E
- 11.0
T_OFF T going High to TBUF going inactive, not driving LL.
XQ4005E
XQ4010E
-
1.8
1.5 1.8
XQ4013E 1.5 1.8
XQ4025E
-
1.8
T_PUS
T going High to LL going from Low to High, pulled up by a single
resistor.⁽¹⁾
XQ4005E
XQ4010E
- 23.0
22.0 29.0
XQ4013E 26.0 32.0
XQ4025E
- 42.0
T_PUF
T going High to LL going from Low to High, pulled up by two
resistors.⁽¹⁾
XQ4005E
XQ4010E
- 10.0
11.0 13.5
XQ4013E 13.0 15.0
XQ4025E
- 18.0
Notes:
1. These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS021 (v2.2) June 25, 2000
www.xilinx.com
5
Product Specification
1-800-255-7778