XQ4010E-4PG191M Datasheet, PDF (16/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

QPRO XQ4000E/EX QML High-Reliability FPGAs
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XQ4000E IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000E devices unless otherwise noted.
-3
-4
Symbol
Description
Min
Max Min Max Units
Propagation Delays (TTL Output Levels)
T_OKPOF Clock (OK) to pad, fast
T_OKPOS Clock (OK) to pad, slew-rate limited
T_OPF Output (O) to pad, fast
T_OPS Output (O) to pad, slew-rate limited
T_TSHZ 3-state to pad High-Z, slew-rate independent
T_TSONF 3-state to pad active and valid, fast
T_TSONS 3-state to pad active and valid, slew-rate limited
Propagation Delays (CMOS Output Levels)
-
6.5
-
7.5
ns
-
9.5
-
11.5
ns
-
5.5
-
8.0
ns
-
8.6
-
12.0
ns
-
4.2
-
10.0
ns
-
8.1
-
10.0
ns
-
11.1
-
13.7
ns
T_OKPOFC Clock (OK) to pad, fast
T_OKPOSC Clock (OK) to pad, slew-rate limited
T_OPFC Output (O) to pad, fast
T_OPSC Output (O) to pad, slew-rate limited
T_TSHZC 3-state to pad High-Z, slew-rate independent
T_TSONFC 3-state to pad active and valid, fast
T_TSONSC 3-state to pad active and valid, slew-rate limited
Setup and Hold Times
-
7.8
-
9.5
ns
-
11.6
-
13.5
ns
-
9.7
-
10.0
ns
-
13.4
-
14.0
ns
-
4.3
-
5.2
ns
-
7.6
-
9.1
ns
-
11.4
-
13.1
ns
T_OOK
T_OKO
T_ECOK
T_OKEC
Clock
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock enable (EC) to clock (OK) setup
Clock enable (EC) to clock (OK) hold
4.6
-
5.0
-
ns
0
-
0
-
ns
3.5
-
4.8
-
ns
1.2
-
1.2
-
ns
T_CH Clock High
T_CL Clock Low
Global Set/Reset⁽³⁾
4.0
-
4.5
-
ns
4.0
-
4.5
-
ns
T_RRO Delay from GSR net to pad
-
11.8
-
15.0
ns
T_MRW GSR width
11.5
-
13.0
-
ns
T_MRO GSR inactive to first active clock (OK) edge
11.5
-
13.0
-
ns
Notes:
1. Output timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall
times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the
“Additional XC4000 Data” section on the Xilinx web site, www.xilinx.com/partinfo/databook.htm.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
16
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DS021 (v2.2) June 25, 2000
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