XQ4010E-4PG191M Datasheet, PDF (26/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4028EX CLB Level-Sensitive RAM Timing Waveforms
WRITE
ADDRESS
T_AS
WE
DATA IN
READ WITHOUT WRITE
TILO
X,Y OUTPUTS VALID
T_WC
T_WP
T_AH
TDS
TDH
REQUIRED
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
TICK
CLOCK
XQ,YQ OUTPUTS
READ DURING WRITE
WRITE ENABLE
DATA IN
(stable during WE)
X,Y OUTPUTS
VALID (OLD)
VALID
T_WO
TCH
T_CKO
TWP
VALID (NEW)
TDH
VALID
DATA IN
(changing during WE)
X,Y OUTPUTS
OLD
VALID
(PREVIOUS)
TWO
VALID
(OLD)
TDO
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
TWP
WRITE ENABLE
TWCK
TDCK
DATA IN
NEW
VALID
(NEW)
CLOCK
XQ,YQ OUTPUTS
Figure 1:
T_CKO
DS021_03_060100
26
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification