XQ4010E-4PG191M Datasheet, PDF (13/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
T_ICKOF
(Max)
Description
Global clock to output (fast) using OFF
TPG
OFF
Global Clock-to-Output Delay
Device
XQ4005E
XQ4010E
XQ4013E
XQ4025E
-3
-
10.9
11.0
-
-4
14.0
16.0
16.5
17.0
Units
ns
ns
ns
ns
T_ICKO
(Max)
DS021_04_060100
Global clock to output (slew-limited) using OFF
TPG
OFF
Global Clock-to-Output Delay
XQ4005E
-
18.0
ns
XQ4010E
14.9
20.0
ns
XQ4013E
15.0
20.5
ns
XQ4025E
-
21.0
ns
T_PSUF
(Min)
DS021_04_060100
Input setup time, using IFF (no delay)
Input
Setup
and Hold
Time
D
T_PG
IFF
XQ4005E
-
2.0
ns
XQ4010E
0.2
1.0
ns
XQ4013E
0
0.5
ns
XQ4025E
-
0
ns
T_PHF
(Min)
DS021_05_060100
Input hold time, using IFF (no delay)
Input
Setup
and Hold
Time
D
TPG
IFF
XQ4005E
-
4.6
ns
XQ4010E
5.5
6.0
ns
XQ4013E
6.5
7.0
ns
XQ4025E
-
8.0
ns
T_PSU
(Min)
DS021_05_060100
Input setup time, using IFF (with delay)
Input
Setup
and Hold
Time
D
TPG
IFF
XQ4005E
-
8.5
ns
XQ4010E
7.0
8.5
ns
XQ4013E
7.0
8.5
ns
XQ4025E
-
9.5
ns
T_PH
(Min)
DS021_05_060100
Input hold time, using IFF (with delay)
Input
Setup
and Hold
Time
D
T_PG
IFF
XQ4005E
-
XQ4010E
0
XQ4013E
0
XQ4025E
-
0
ns
0
ns
0
ns
0
ns
Notes:
1. OFF = Output Flip-Flop
2. IFF = Input Flip-Flop or Latch
DS021_05_060100
DS021 (v2.2) June 25, 2000
www.xilinx.com
13
Product Specification
1-800-255-7778