XQ4010E-4PG191M Datasheet, PDF (30/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

QPRO XQ4000E/EX QML High-Reliability FPGAs
R
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
-4
Symbol
Description
Min
Units
Setup Times
T_PICK Pad to Clock (IK), no delay
T_PICKP Pad to Clock (IK), partial delay
T_PICKD Pad to Clock (IK), full delay
T_PICKF Pad to Clock (IK), via transparent Fast Capture Latch, no delay
T_PICKFP Pad to Clock (IK), via transparent Fast Capture Latch, partial delay
T_POCK Pad to Fast Capture Latch Enable (OK), no delay
T_POCKP Pad to Fast Capture Latch Enable (OK), partial delay
Setup Times (TTL or CMOS Inputs)
2.5
ns
10.8
ns
15.7
ns
3.9
ns
12.3
ns
0.8
ns
9.1
ns
T_ECIK Clock Enable (EC) to Clock (IK)
Hold Times
0.3
ns
T_IKPI
Pad to Clock (IK), no delay
0
ns
T_IKPIP Pad to Clock (IK), partial delay
0
ns
T_IKPID Pad to Clock (IK), full delay
0
ns
T_IKPIF Pad to Clock (IK) via transparent Fast Capture Latch, no delay
0
ns
T_IKFPIP Pad to Clock (IK) via transparent Fast Capture Latch, partial delay
0
ns
T_IKFPID Pad to Clock (IK) via transparent Fast Capture Latch, full delay
0
ns
T_IKEC Clock Enable (EC) to Clock (IK), no delay
0
ns
T_IKECP Clock Enable (EC) to Clock (IK), partial delay
0
ns
T_IKECD Clock Enable (EC) to Clock (IK), full delay
0
ns
T_OKPI Pad to Fast Capture Latch Enable (OK), no delay
0
ns
T_OKPIP Pad to Fast Capture Latch Enable (OK), partial delay
0
ns
Notes:
1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
2. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on page 28.
30
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DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification