XQ4010E-4PG191M Datasheet, PDF (31/36 Pages) Xilinx, Inc – QPRO XQ4000E/EX

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QPRO XQ4000E/EX QML High-Reliability FPGAs
FXQ4028EX IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values
apply to all XQ4000EX devices unless otherwise noted.
-4
Symbol
Description
Min
Max
Propagation Delays (TTL Output Levels)
T_OKPOF Clock (OK) to pad, fast
T_OPF
Output (O) to pad, fast
T_TSHZ 3-state to pad High-Z, slew-rate independent
T_TSONF 3-state to pad active and valid, fast
T_OKFPF Output MUX select (OK) to pad
T_CEFPF Fast path output MUX input (EC) to pad
T_OFPF Slowest path output MUX input (EC) to pad
Setup and Hold Times
-
7.4
-
6.2
-
4.9
-
6.2
-
6.7
-
6.2
-
7.3
T_OOK
T_OKO
T_ECOK
T_OKEC
Clocks
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock enable (EC) to clock (OK) setup
Clock enable (EC) to clock (OK) hold
0.6
-
0
-
0
-
0
-
T_CH
Clock High
T_CL
Clock Low
Global Set/Reset
3.5
-
3.5
-
T_MRW Minimum GSR pulse width
13.0
-
T_RRI
Delay from GSR input to any pad
30.2
-
Notes:
1. Output timing is measured at TTL threshold, with 35 pF external capacitive loads.
2. For CMOS output levels, see the "XQ4028EX Output Level and Slew Rate Adjustments" on page 27.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS021 (v2.2) June 25, 2000
www.xilinx.com
31
Product Specification
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