WP484 Datasheet, PDF (9/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
length is less than 1in when breaking out of the FPGA/DRAM device. To further ensure reliable
signal integrity, the following guidelines must also be followed:
• 2X or greater spacing after the breakout region.
• Total PCB interconnect length of 4in from the FPGA to the DRAM using an FR4-type substrate.
CLOCK, ADDR, CMD, and CONTROL Signals
The CLOCK, ADDR (address), CMD (command), and CONTROL signals are typically point to
multi-point connections and require a unique topology termed Fly-by. Fly-by can be envisioned as
a daisy-chain connection without stubs. These signals are unidirectional and are driven from the
FPGA to the memory device. The differential clock net is used as the reference signal for timing
analysis.
External Termination
ODT is not available for these nets, and an external discrete termination is required. The
recommended form typically consists of a resistor placed at the far end, past the last memory
device, and pulled up to V_TT (V_VDDQ /2). The value of the pull-up resistor and the impedance of the
interconnecting traces depends on the number of devices on the net. These values are usually
optimized through simulation. Xilinx provides the necessary FPGA IBIS models for customers who
want to perform their own simulation analysis to further optimize these values.
Xilinx recommends the following guidelines for low cost design.
• Xilinx recommends routing the ADDR/CMD/CTRL signals with a 50Ω characteristic impedance
trace using a 50Ω fly-by termination resistor to V_TT (V_VDDQ/2) at the far end. This should be
applicable for most cases.
• For the CLK differential pair, it is recommended to implement a differential trace impedance of
100Ω using two separate 50Ω pull-up resistors to V_VDDQ and a DC blocking capacitor. Figure 6
shows a schematic representation for clock fly-by termination.
WP484 (v1.0) September 27, 2016
www.xilinx.com
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