WP484 Datasheet, PDF (4/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

X-Ref Target - Figure 3
DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
Ball Pitch
Available Routing
Distance
Ball Pitch
Available Routing
Distance
Pad
Diameter
Pad
Diameter
Pad
Diameter
Pad
Diameter
TS
TS
TW
TW = Trace Width
TS = Trace Spacing
TS TS TS
TW TW
Figure 3: Definition of Routes per Channel on Top/Bottom Layers
WP484_03_090316
For a 0.5mm pitch package, the pad size and the package pitch dimensions limit the PCB designer
to a single trace between the BGA pads. However, PCB designers have the flexibility to go either for
a single-trace or a dual-trace breakout when opting for a 0.8mm or a 1mm pitch package.
The approximate number of layers required to route Artix-7 and Spartan-7 FPGAs are shown in
Table 1 and Table 2, respectively.
Table 1: Artix-7 FPGAs: Approximate Signal Layers per # of BGA Balls
BGA Balls
Ball Pitch (mm)
Signal Layer Counts
(All Available I/Os Routed)
Routes per Channel:
Two Traces
One Trace
236
0.5
NA
3
256
1.0
2
3
324
0.8
2
3
325
0.8
2
3
484
0.8
3
4
484
1.0
2
4
676
1.0
3
5
1156
1.0
3
6
WP484 (v1.0) September 27, 2016
www.xilinx.com
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