WP484 Datasheet, PDF (5/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
Table 2: Spartan-7: Approximate Signal Layers per # of BGA Balls
BGA Balls
Ball Pitch (mm)
Signal Layer Counts
(All Available I/Os Routed)
Routes per Channel:
Two Traces
One Trace
144
0.5
N/A
2
196
0.5
N/A
2
225
0.8
2
3
324
0.8
2
3
484
1.0
2
4
676
1.0
3
5
The critical factors to consider when breaking out signals underneath a high-density BGA include:
• Dimensions of surface land pads
• PTH size and the corresponding pad/anti-pad dimensions
• Trace width and spacing requirements
• Number of signal layers available
The number of options available for a PCB designer during layout is primarily driven by the
package pitch. PCB designers with a goal to minimize the PCB layer count at the expense of cost
can use advanced fabrication techniques like micro vias, blind vias, and buried vias in addition to
using thinner trace widths. However, these advanced fabrication techniques are not mandatory to
ensure the success of a DDR3 design. Following Figure 4 is a brief description of the various
industry terms, along with an approximation of cost adders applied to the standard PCB fabrication
cost. Figure 4 shows the various via types.
WP484 (v1.0) September 27, 2016
www.xilinx.com
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