WP484 Datasheet, PDF (10/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
X-Ref Target - Figure 6
DRAM #1 DRAM #2
VDDQ
C = 0.01 μF
Memory
Controller
Via
MAIN
Via
PKG Length
Breakout
Breakout
Ʊ
RTT = 50
Via
Via
L4
STUB
Ʊ
RTT = 50
Via
MAIN
Via
PKG Length
Breakout
Breakout
Via
Via
L4
STUB
Figure 6: Fly-By Termination
WP484_06_090316
Figure 7 shows V_TT capacitor placement to ensure reliable power integrity. Xilinx recommends
placing at least one 0.1µf capacitor tied to V_TT for every four termination resistors.
X-Ref Target - Figure 7
WP484_07_090316
Figure 7: V_TT Capacitor Placement
In addition, Xilinx recommends keeping the interconnect length between the DRAMs and the stub
length from the last DRAM to fly-by termination resistor within 0.75in.
WP484 (v1.0) September 27, 2016
www.xilinx.com
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