WP484 Datasheet, PDF (3/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
Routing Channels are the total number of available routing paths out of the BGA—e.g., (Number
of BGA balls on one side –1) × four sides.
Figure 2 shows a sample 5 × 5 BGA ball out, resulting in a total of sixteen total routing channels.
Number of BGA balls on one side = 5
Routing Channels = ( 5 – 1 ) × 4
X-Ref Target - Figure 2
WP484_02_090316
Figure 2: Definition of Routing Channel
Routes per Channel are typically one or two, depending on the number of traces that can be routed
between the BGA pads on the top/bottom layer. From a signal integrity standpoint, adhering to
design for manufacturing (DFM) guidelines is critical to assure meeting the nominal trace
impedance requirements. Figure 3 shows a schematic representation of routes per channel. The
routes per channel on the inner layers depend on the spacing between the vias, taking into account
the drill-to-copper specifications.
WP484 (v1.0) September 27, 2016
www.xilinx.com
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