WP484 Datasheet, PDF (8/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
X-Ref Target - Figure 5
VDD / VREF
Clock
(differential)
Address
ClKP,CKN_
ADDR<15,0>
VDD / VREF
Pull-ups
VTT
Rtt
Command/
Control
DataStrobe
(differential)
DataMask
CKE, CS, ODT, RAS, CAS, WE, BAO-2
DQS0, DQS1, DQS2, DQS3
DM0, DM1, DM2, DM3
ODT
Termination
Data
DQ<7,0>, DQ<15,8>
DQ<23,16>, DQ<31,24>
Memory
Module
FPGA
WP484_05_090316
Figure 5: Architecture and Interface Technology Common to DDR2 and DDR3 Memory
This section provides high-level layout guidelines for enabling a low cost PCB design. The key
challenge to a successful memory layout is:
• Breaking out all the data and address signals on minimum number of routing layers
• Ensuring a robust signal integrity by minimizing crosstalk, signal reflections due to impedance
discontinuities, etc.
Waveform Integrity
DQ, DM, DQS nets are typically point-to-point connections. These nets are bidirectional, with data
being latched on both the rising and falling edges of their associated data strobe signals. Xilinx
recommends the following:
• Choose a FPGA driver setting with an output impedance closest to the transmission line
impedance.
• Route these signals with a 50Ω characteristic impedance on the PCB all the way from the FPGA
to the memory device.
• Enable the on-die termination (ODT) setting that is closest to 50Ω on the DRAM to minimize
reflections during WRITE operation.
• Enable termination on FPGA during READ operation to ensure a matched termination for
bidirectional high data rate operation
To minimize crosstalk, it is always advisable to space the signals far apart and minimize the via
length during layer transitions. However, the area under the FPGA and DRAM device are
space-constrained, making it difficult to space the signals far apart. To ease PCB layout, Xilinx
allows a minimum spacing—i.e., 1X spacing—in the breakout region. 1X spacing refers to the air
gap between the traces equal to the trace width. This spacing can be maintained provided the trace
WP484 (v1.0) September 27, 2016
www.xilinx.com
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