WP484 Datasheet, PDF (11/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
Delay Matching of Signal Nets
While trace length, impedance, and terminations can be designed for optimal waveform integrity,
it is also important to ensure that the delay between the synchronous nets be matched very closely.
All DQ and DM nets in a byte lane must be matched to their associated DQS nets, taking into
account the package flight time differences.
Xilinx recommends the following:
• All DQ/DM nets should be matched to their associated DQS nets to within ±15ps for
DDR2/DDR3 interfaces at 800Mb/s
• All DQ/DM nets should be matched to their associated DQS nets to within ±10ps for
DDR2/DDR3 interfaces at 1,066Mb/s
• For unidirectional signals, all ADDR/CMD/CTRL signals must be matched to the CLK signal. It is
a good design practice to match each transmission line segment (FPGA to DRAM1, FPGA to
DRAM2, FPGA to fly-by termination resistor, etc.) to within a reasonable tolerance of ±25ps.
Conclusion
Xilinx Artix-7 and Spartan-7 devices are proven to interoperate with DDR2/3 speeds at up to
1,066Mb/s and 800Mb/s, respectively. The purpose of this white paper is to provide high-level
guidance on layer count estimation and the cost implications of using advanced fabrication
technologies. In addition, the paper presents high-level layout guidelines for low-cost PCB design,
which help optimize I/O performance and reduce the risk of performance issues. For complete
details, refer to the device data sheets.[Ref 2][Ref 3]
References
1. Xilinx User Guide UG1099, Recommended Design Rules and Strategies for BGA Devices
2. Xilinx Data Sheet DS181, Artix- 7 FPGA Data Sheet: DC and AC Switching Characteristics
3. Xilinx Data Sheet DS189, Spartan- 7 FPGA Data Sheet: DC and AC Switching Characteristics
WP484 (v1.0) September 27, 2016
www.xilinx.com
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