WP484 Datasheet, PDF (2/12 Pages) Xilinx, Inc – DDR2/DDR3 Low-Cost PCB Design

DDR2/DDR3 Low-Cost PCB Design Guidelines for Artix-7 and Spartan-7 FPGAs
Introduction
Artix-7 and Spartan-7 devices come in a wide variety of packages that are designed for maximum
performance and maximum flexibility. The Spartan-7 FPGA packages are available in small package
footprint with package sizes ranging from 8mm to 27mm, while the Artix-7 FPGA packages vary
from 10mm to 35mm. The packages are available in a 1.0mm, 0.8mm, and 0.5mm package pitches,
respectively. Package pitch is defined as the distance between consecutive balls on a BGA package,
measured from center to center, as shown in Figure 1.
X-Ref Target - Figure 1
0.5mm
0.8mm
1.0mm
0.5mm
0.8mm
1.0mm
Figure 1: Package Pitch
WP484_01_090916
In general, as the pitch size decreases, the challenges for PCB routing increase because there is less
room to route traces and vias between the package balls.
Layer Count Estimation and Cost Trade-Offs
A quick way to estimate the number of routing layers required to fully break out signal pins from
the FPGA is to use Equation 1:
Layers = ^{---------------S--i-g---n--a---l---P---i-n---s---(---I-/--O---s--,---M----G---T---s----)--------------}
Routing Channels • Routes per Channel
Equation 1
For Xilinx® cost-optimized FPGAs, the number of signal pins is approximately 60% of the total
number of BGA balls. The other 40% includes power and ground signals that are most often routed
directly down to the planes by vias. This is assuming full I/O utilization. If fewer I/Os are used, then
the number of signals to route decreases accordingly.
WP484 (v1.0) September 27, 2016
www.xilinx.com
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